xref: /llvm-project/polly/test/CodeGen/MemAccess/update_access_functions___%loop1---%exit.jscop (revision 35f7020098773816f151c2c1da7b4dfc11041126)

{
   "context" : "[arg] -> {  : -9223372036854775808 <= arg <= 9223372036854775807 }",
   "name" : "%loop1---%exit",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "[arg] -> { Stmt_loop1[i0] -> MemRef_A[1 + i0] }"
            }
         ],
         "domain" : "[arg] -> { Stmt_loop1[i0] : 0 <= i0 <= -2 + arg }",
         "name" : "Stmt_loop1",
         "schedule" : "[arg] -> { Stmt_loop1[i0] -> [0, i0] }"
      },
      {
         "accesses" : [
            {
               "kind" : "read",
               "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_A[1 + i0] }"
            },
            {
               "kind" : "write",
               "relation" : "[arg] -> { Stmt_loop2[i0] -> MemRef_val[] }"
            }
         ],
         "domain" : "[arg] -> { Stmt_loop2[i0] : 0 <= i0 <= -2 + arg }",
         "name" : "Stmt_loop2",
         "schedule" : "[arg] -> { Stmt_loop2[i0] -> [1, i0] }"
      },
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_A[1 + i0] }"
            },
            {
               "kind" : "read",
               "relation" : "[arg] -> { Stmt_loop3[i0] -> MemRef_val[] }"
            }
         ],
         "domain" : "[arg] -> { Stmt_loop3[i0] : 0 <= i0 <= -2 + arg }",
         "name" : "Stmt_loop3",
         "schedule" : "[arg] -> { Stmt_loop3[i0] -> [2, i0] }"
      }
   ]
}